1. Field of Invention
The present invention relates to a method for producing a semiconductor device and an apparatus for producing a semiconductor device.
The semiconductor includes silicon semiconductor or compound semiconductor. The semiconductor device includes a memory IC (integrated circuit), a logic circuit IC, and a thin film transistor IC.
The method for producing the semiconductor device includes the following heat treatments: (a) a CVD (chemical vapor deposition) under normal or reduced pressure, for forming a film or layer, on a wafer used for the above mentioned semiconductor device, which film or layer consists of a semiconductive material, insulating material, metal, super-conductive material; (b) a diffusion, improvement of film material, flattening of the film under the presence of a protective gas such as Ar, He, N.sub.2 or the like; (c) polycrystallizing an amorphous Si layer which is formed on a glass substrate; (d) RTP (rapid thermal processing) annealing of a high-dielectric constant film, such as BST (barium strontium titanate), ST (strontium titanate), Ta.sub.2 O.sub.5 or the like for improving the film properties of these materials; (e) RTP annealing of a film of WSi.sub.2, TiSi.sub.2 or the like for decreasing the resistivity of these materials; (f) RTP annealing of a film of SiO.sub.2, PSG, BPSG, SiN, SiON or the like for flattening and densifying it; (g) RTP annealing of a ferro-dielectric film such as Y-1, BST or the like; (h) activation of the implanted ions; (i) formation of a thin film on a Si substrate by its reaction with a reaction gas, such as a SiO.sub.2, SiON, SiO film or the like; and (j) nitrifying the surface of a SiO.sub.2 film to an extreme thinness thickness of from 1 to 5 angstroms.
The method according to the present invention attains such uniform properties over the wafer as film thickness, impurity concentration and diffusion depth which have a relationship with the performance of a semiconductor device, without incurring the generation of slip lines in a single crystalline substrate.
The production apparatus according to the present invention enables the implementation of the above described methods using a vertical or horizontal hot-wall type heating furnace.
2. Description of Related Arts
U.S. Pat. No. 5,387,557 (hereinafter referred to as the U.S. patent) proposed by the present applicant discloses a dual-tube type RTP apparatus for producing a semiconductor device using a vertical hot-wall heating furnace, whose temperature uniformity is excellent. This RTP apparatus comprises a dual reaction tube made of quartz and consisting of an inner tube and an outer tube, an introduction conduit of the reaction gas opened at the bottom portion of the inner tube, and an evacuation conduit opened at the bottom portion of the outer tube, or an annular gas channel for withdrawing the reaction gas, formed between the inner and outer tubes arranged concentrically. These parts are heated by a resistance heater(s). A wafer(s) is first held at a low temperature, where the diffusion length extends only slightly, for example, 750.degree. C. or less, and is then rapidly moved upwards into a high-temperature region, where it is brought into contact, for a predetermined short period of time, with the reaction gas which flows upwards in the inner tube. Immediately after the reaction, the wafer(s) is moved by a wafer-holder into the low-temperature region positioned in a bottom portion of the furnace.
A Si wafer having a diameter of 150 mm was subjected to ion implantation under the condition of BF.sub.2, 3.0E15/cm.sup.2, and 2.30 keV. Subsequently, the so ion-implanted wafer was preliminarily held at low temperature and then annealed at 950.degree. C. for 2 minutes in the RTP apparatus disclosed in the U.S. Patent. The sheet resistance of the wafers was approximately 220 and its distribution in the surface was within .+-.1% (the average value of five wafers). The ordinary heat treatment method without holding at low temperature was carried out at 850.degree. C. for 120 minutes. The sheet resistance of the wafers was 310.OMEGA.. Similar annealing was carried out at 850.degree. C. for 30 minutes. Then the sheet resistance was 400.OMEGA.. This value implies that the diffused, interstitial impurities are not thoroughly converted to the substitutional impurities and, hence, the impurities do not thoroughly contribute to the conduction of current. The distribution of the sheet resistance on the surface was approximately 1% in the cases of the ordinary heat treatment method.
In order to improve the temperature distribution of a plurality of wafers which are heat-treated in a conventional vertical hot-wall heat-treating furnace, the distance between the wafers has been widened. The present inventor carried out experiments in a conventional vertical hot-wall furnace and considered the temperature distribution of a wafer(s) heated in such a furnace so as to ascertain whether there are any limitations involved in the prior art with respect to the temperature distribution. This experiment is described with reference to FIG. 13.